This manual is for uz80as (Micro Z80 assembler) version
2.02 (updated 19 June 2023).
uz80as is an assembler for the Zilog Z80 and several other microprocessors.
It accepts source files with the same syntax accepted by the Telemark Cross Assembler (TASM), with only minor differences.
Currently, uz80as can assemble for these microprocessors:
uz80as is free software.
The latest version of the program, source code and documentation can be found at https://jorgicor.niobe.org/uz80as.
For bug reports and suggestions, you can write to Jorge Giner at jorge.giner@hotmail.com .
Each line of the source file must be a an assembler statement or a preprocessor directive. Mathematical expressions can be used where a number is expected.
Each assembler statement must follow this format:
label operation operands comment
For example:
START LD A,5 ; Load 5 into A
Everything that starts with an alphabetic character at the first column is considered a label.
A label must be separated by the rest of fields on the line by a space, tab or a colon ‘:’.
The operation can be a microprocessor instruction or an assembler directive (assembler directives start with a dot ‘.’).
Assembler directives can start at column 1, as they start with a dot ‘.’ and cannot be taken for a label. But a microprocessor instruction cannot start at column 1, or it would be taken as a label.
The operation must be separated by the operands (if any) with a space.
The rest of the line is the operands field until we reach the end of line or a semicolon ‘;’.
If we find a semicolon ‘;’ character at any position, the rest of the line is ignored.
All of these fields are optional except the operands field which, if present, must be preceded always by an operation field.
These are examples of statements:
; Program version 3
.ORG 4000
LABEL LD A,5
ADD 6 ; Add 6
MEM .FILL 2
.END ; End of program
A backslash character ‘\’ can be used to simulate a new line. Then it is possible to put one or more statements on the same line:
LD A,B\ LD B,C\ LD C,A
Remember that, as the backslash character simulates a new line, if the first character after it is alphabetic, it will be considered as a label. That is why we leave a space after the backslash in the example above.
The label field must start with an character from ‘A’ to ‘Z’. The next characters, if any, must be letters, numbers, underscores ‘_’ or periods ‘.’. Any other character terminates the label, and it must be a space, a tab or a colon ‘:’.
A label with more than 31 characters will issue an error.
Labels are case sensitive, so ‘START’ is different from ‘start’.
Each label has a value, which is:
.EQU directive follows the label, the label takes the value of the expression introduced by the .EQU.
.ORG directive follows the label, the label takes the address that the .ORG directive is setting.
The operation field is a microprocessor instruction opcode (like ADD, SUB, CALL, etc) or an assembler directive (like .ORG, .EQU, etc).
If it is a microprocessor instruction, it cannot start at the first column of the line, because in that case it would be considered a label.
Assembler directives can start at any column as they start with a dot ‘.’.
The operands field contains the operands for the instruction or the arguments of assembler directives. They can involve expressions, addressing modes, etc.
A comment starts with a semicolon ‘;’ character and extends to the end of the line. It can be the only field on a line.
Wherever a number is accepted in the operands of an instruction or directive, you can use an expression instead. An expression is formed using labels, constants, the program counter symbol, operators and parenthesis.
A decimal numeric constant is expressed normally by the decimal number, optionally followed by the ‘D’ suffix.
An hexadecimal constant is expressed by using the ‘$’ prefix or by using the ‘H’ suffix. It can be formed by the digits from ‘0’ to ‘9’ and the letters from ‘A’ to ‘F’. Note that an hexadecimal constant that uses the suffix form and starts with a letter must be prefixed with a ‘0’ digit or it will be taken as a label.
An octal constant is expressed by using the ‘@’ prefix or by using the ‘O’ suffix. It can be formed by the digits from ‘0’ to ‘7’.
Binary constants are expressed using the ‘%’ prefix or by using the ‘B’ suffix.
All the letters for hexadecimal constants or suffixes can be in lower case as well.
For example, all these values represent the decimal number 255, using different notations:
Decimal 255 or 255D Hexadecimal $FF or 0FFH Octal @377 or 377O Binary %11111111 or 11111111B
Character constants are single characters enclosed in single quotes, for example: ’c’.
The ASCII code of the character is used as the value.
Non-printable characters cannot be expressed this way, but you can use the .TEXT directive instead.
String constants are one or more characters enclosed in double quotes, for example: "This is a string." .
String constants are not allowed in expressions but can be used with certain directives, like .TITLE, .TEXT, .BYTE, .DB, .WORD and .DW.
String constants can contain escape sequences to represent non-printable characters.
An escape sequence starts with the backslash ‘\’ character:
\nLine feed.
\rCarriage return.
\bBackspace.
\tTab.
\fForm feed.
\\Backslash.
\"Double quote.
You can express any other character by using the backslash ‘\’ followed by an octal constant using exactly 3 digits.
For example, \377 represents the character value 255, and is the maximum octal value representable using a backslash.
Examples:
"This ends with a newline.\n" "\tThe name is \"Bye Bug\"."
In an expression you can use the value of the current program counter which is the memory address that will be assigned to the line we are assembling. You can use the dollar character ‘$’ or the asterisk ‘*’ to represent the current program counter.
For example:
START LD HL,START
is equivalent to
START LD HL,$
All operations are done using at least 32 bit signed precision. An expression is evaluated left to right and there is no operator precedence. Use parenthesis if you want to change the precedence. For example:
1 + 2*3 + 4
will be evaluated as:
((1 + 2) * 3) + 4
Use parenthesis to indicate the desired order of evaluation:
1 + (2*3) + 4
Summary of operators:
+Addition.
-Subtraction or negation.
*Multiplication.
/Integer division.
%Modulo.
<<Logical left shift.
>>Arithmetic right shift (the sign bit fills new positions).
~One’s complement (invert all bits).
= or ==Equal. The result is 1 if equal, 0 if not.
!=Not equal. The result is 1 if not equal, 0 if equal.
<Less than. The result is 1 if a < b, 0 otherwise.
<=Less than or equal. The result is 1 if a <= b, 0 otherwise.
<Greater than. The result is 1 if a > b, 0 otherwise.
<=Greater than or equal. The result is 1 if a >= b, 0 otherwise.
&Binary ‘AND’.
|Binary ‘OR’.
^Binary ‘XOR’.
For the shift operators >> and <<, the second operand specifies the number of bits to shift the first operand.
The assembler directives are distinguished from the microprocessor instructions because they begin with a dot character ‘.’. They are commands to control the assembly process.
[label] .BLOCK expr
expr is evaluated and its value added to the current program counter.
Thus .BLOCK n is equivalent to .ORG $+n.
[label] .BYTE expr [, expr ...]
The .BYTE directive is supplied with one or more expressions separated
by commas.
Each expr can be a numeric expression or a string constant.
If the expression is numeric, the lower eight bits of the result are output to the object file.
If the expression is a string, for each character its ‘ASCII’ value is output to the object file.
START .BYTE 'a', "hello", 5 - START
Note that the program counter symbol used in any of the expressions refers to the value the program counter had at the beginning of the line, and not at the start of each expression.
You can use .DB as an alternative name for .BYTE.
[label] .CHK expr
The checksum directive takes all the bytes from the address expr up to the current address, and combines them using an exclusive OR operation (XOR).
The result (a byte) is output to the object file.
The address defined by expr must be in the range [0, current program counter[.
For example, this will output in the object file the bytes 1, 2, 3, 4 and the result of CHK, which is 4:
START .DB 1, 2, 3, 4
.CHK START
Enables the generation of line numbers, opcodes, etc. in the listing file.
This is enabled by default, but can be disabled using the .NOCODES directive.
.DB is an alternate name for .BYTE.
.DS is an alternate name for .BLOCK.
.DW is an alternate name for .WORD.
[label] .ECHO expr [label] .ECHO string
Outputs to the console (stderr) an expression value or a string.
For example,
.ECHO "The code size is " .ECHO PRG_END - PRG_START .ECHO " bytes long.\n"
may result in:
The program size is 237 bytes long.
The .EJECT directive is accepted but not implemented.
In TASM, forces a new page in the listing file.
[label] .END [addr]
The .END directive should be the last one in the program.
It is accepted only for compatibility with TASM but, if not used, we will only issue a warning.
If it is present, it is an error to use any directive or instruction that generates code after it.
It is an error to have more than one .END directive.
label .EQU expr
Normally, a label takes the value of the current program counter, but you can assign the result of an expression to a label. The label is mandatory in this case.
An alternative syntax uses the equal sign ‘=’ instead of .EQU:
label = 25
[label] .EXPORT label [, label...]
With the .EXPORT directive you can specify a list of labels that will be exported to a symbol export file.
The symbol export file will contain the labels and their values as equates.
For example:
.EXPORT start, func1
could produce in the symbol export file this equates:
start .EQU $4000 func1 .EQU $4008
[label] .FILL number_of_bytes [, fill_value]
Outputs number_of_bytes bytes to the output file.
The value output to each byte is the least significant byte of fill_value.
If no fill_value is supplied, the value 255 is used.
It is an error to supply a negative number_of_bytes.
Turns on the output to the listing file.
This is the default.
Use .NOLIST to disable it.
Turns on little endian mode.
When a .WORD directive is found, it will take the 16 lower significant bits of the value, and from these the least significant byte will be output first to the object file, then the most significant byte.
This is the default.
Use .MSFIRST to change this behavior.
This example will output the byte ‘$34’ and then ‘$12’ to the output file.
.LSFIRST
.WORD $1234
Turns on big endian mode.
When a .WORD directive is found, it will take the 16 lower significant bits of the value, and from these the most significant byte will be output first to the object file, then the least significant byte.
Use .LSFIRST to change this behavior.
This example output the byte ‘$12’ and then ‘$34’ to the output file.
.MSFIRST
.WORD $1234
Disables the generation of line numbers, opcodes, etc. in the listing file.
Use .CODES to enable it again.
Turns off the output to the listing file.
Use .LIST to enable it again.
[label] .ORG expr [label] *=expr [label] $=expr
Sets the program counter to the value of expr, which must be in the range [0, 65536].
expr can have references to the current program counter.
For example, to advance the program counter to the next 256 boundary, we can use:
.ORG ($ + 0FFH) & 0FF00H
Note that a label that is used with an .ORG directive will take the value of the program counter set by the .ORG.
You can use .ORG or the alternative forms *= and $=.
[label] .TEXT string
Outputs the ASCII value of each character of the supplied string to the object file as a byte.
Special characters can be embedded in the string using escape sequences.
See String constants.
msg1 .TEXT "Enter the file name\n" msg2 .TEXT "Say \"YES\" or \"NO\""
Accepted but currently ignored.
.TITLE "Program version 1.2"
.TITLE "Subtitle"
[label] .WORD expr [, expr ...]
The .WORD directive accepts an expression or a list of expressions, and outputs the 16 bit value of each expression as two bytes.
The default is to output the least significant byte first.
You can change this behavior with the .MSFIRST and .LSFIRST directives.
Note that if you use the program counter symbol (‘$’) in any expression in a .WORD directive, it takes the value of the program counter at the beginning of the line, and not its value at the start of each expression.
For example:
START .EQU 0
.WORD $1234, $
will output:
$34 $12 $00
and not:
$32 $12 $02
The preprocessor directives can be used to assemble or not some parts of the source, to include text from other files to assemble, and to define macros that can cause text substitution.
#DEFINE macro_name[(arg_label [, arg_label ...])] [macro_definition]
The #DEFINE directive is used to define a macro name.
Macro names can be used for text substitution.
For example, you can define a label to be expanded to arbitrary text prior compilation:
#DEFINE STARTLO (START & 255)
.DB STARTLO+1
When the assembler finds STARTLO, it will substitute it by the text (START & 255), so it will finally assemble this text:
.DB (START & 255)+1
The substitution is recursive. For example:
#DEFINE STARTLO (START & 255)
#DEFINE STARTLO_PLUS_1 (STARTLO+1)
.DB STARTLO_PLUS_1
This will expand first to:
.DB (STARTLO+1)
And then to:
.DB ((START & 255)+1)
Note that you can define a macro label that expands to no text:
#DEFINE VOID
.DB 5
VOID
.DB 6
And you can make synonyms for directives to, for example, allow to compile the syntax from other assemblers.
For example, imagine an assembler which does not use directives that begin with a dot as we do.
To assemble a source that was written for that assembler with uz80as, you can use a set of defines at the beginning of your source file, and use them later:
#DEFINE DB .DB
#DEFINE DW .DW
...
DB 5, 6, 7
You can define macros with arguments, for example:
#DEFINE ADDMAC(x,y) ((x)+(y))
.DB ADDMAC(5,6)
This works first by taking the text of the ADDMAC macro:
((x)+(y))
and then searches for x in this text and substitutes it by 5.
Next, finds y and substitutes it by 6.
((5)+(6))
Finally, the resulting text is substituted in the original location:
.DB ((5)+(6))
Note that if you do not supply a parameter, nothing will be substituted:
.DB ADDMAC(5)
will expand into:
.DB ((5)+(y))
#DEFCONT can be used to add more text to the previous defined macro.
The macro text will always form an unique line, so remember to use the backslash character if you are forming multiline statements:
#DEFINE ADDMAC(x,y) LD A,x #DEFCONT \ LD B,y #DEFCONT \ ADD B
#INCLUDE "filename"
The #INCLUDE directive is used to include the text of another file
to be assembled.
For example, if the file ‘common.h’ is:
.DB 5
and the file ‘prg.asm’ is:
#include "common.h"
.DB 6
the assembler will compile
.DB 5
.DB 6
#IF expr
The #IF directive evaluates the supplied expression.
If the value of the expression is zero, the next lines are ignored by the assembler, until an #ENDIF or an #ELSE directive is found.
If the value of the expression is not zero, the next lines are assembled normally, until an #ENDIF or #ELSE directive is found.
In this case, if we find an #ELSE directive, the next lines after the #ELSE will be ignored.
In this example, as the expression evaluates to something different than zero, the line LD A,1 will be assembled and LD A,0 ignored:
ASSEMLE .EQU 1
#IF ASSEMBLE
LD A,1
#ELSE
LD A,0
#ENDIF
On the other hand, here the opposite will happen:
ASSEMLE .EQU 1
#IF !ASSEMBLE
LD A,1
#ELSE
LD A,0
#ENDIF
Note that #IF directives can be nested:
TRUE .EQU 1
FALSE .EQU 0
#IF TRUE
#IF FALSE
LD A,0
#ELSE
LD A,1
#ENDIF
#ELSE
#IF TRUE
LD A,2
#ELSE
LD A,3
#ENDIF
#ENDIF
In this example, this code will be assembled:
LD A,1
#IFDEF macro_name
#IFDEF is like #IF, but tests if a macro name has been defined.
#DEFINE SPECTRUM
#IFDEF SPECTRUM
CALL spectrum_fun
#ELSE
CALL amstrad_fun
#ENDIF
will assemble:
CALL spectrum_fun
#IFNDEF is like #IFDEF, but tests if a macro name has not been defined.
Used to end a section that began with an #IF, #IFDEF or IFNDEF directive.
Used to end a section that began with an #IF, #IFDEF, IFNDEF or #ELSE directive.
uz80as [OPTION]... ASM_FILE [OBJ_FILE [LST_FILE [EXP_FILE]]]
Where:
ASM_FILESource file.
OBJ_FILEGenerated file with the compiled machine code.
LST_FILEGenerated listing file.
EXP_FILEGenerated symbol export file.
For example, to assemble program.asm you can use:
uz80as program.asm
If there are no errors, this will generate the file program.obj with the binary machine code of the program. Also, the file program.lst will be generated with the listing of the source program, plus more info like line numbers, the value of the program counter at each line, the generated machine code in hexadecimal, etc.
Also, if the source program contains any .EXPORT directive, then the file program.exp will be generated.
You can give different names for these files by specifying their names after the name of the source file. For example, this will generate the object file with the name program.bin, the listing file with the name list.txt and the symbol export file with the name api.asm:
uz80as program.asm program.bin list.txt api.asm
If the symbol export file is explicitly given in the command line, then a symbol export file will be generated even if there are no .EXPORT directives in the source file.
Additional command line options can be used before the these arguments. They are:
-h, --helpDisplay usage information and exit.
-v, --versionDisplay version information and exit.
-f nn, --fill nBy default, the entire memory addressable (64K) is filled by zero.
You can specify a different value to fill the memory.
'nn' must be formed by two hexadecimal digits.
For example, to fill the memory with the value 255 decimal, use '-f FF'.
-dmacro, --define macroDefine a macro.
If the macro is simply a label, you can use -dLABEL.
If it is a macro for text substitution, you have to enclose the macro definition in double quotes. For example: -d"MUL(a,b) (a*b)".
-q, --quietDisables the generation of the listing file.
-x, --extendedAccept an alternative syntax for some instructions.
-u, --undocumentedAccept undocumented instructions.
-t, --target targetSelects the target microprocessor. The default is z80. See --list-targets to know the targets accepted.
-e, --list-targetsDisplays a list of the targets accepted and a brief description.
Limits:
In the places where we can specify an expression, sometimes we require that the labels referenced in the expression have already a well defined value in the first pass of the assembler.
The following directives do not allow to specify a label not already defined at the point where the directive appears in the first pass: #IF, .BLOCK, .END, .EQU, .FILL (number of positions), .ORG.
uz80as only generates binary object files.
uz80as allows for forward references of labels in the first pass of the assembler can differ from TASM. See Implementation-defined features.
TASM always needs a space or a colon ‘:’ character after a label. Anything else is considered an error. So this does not compile in TASM but it is accepted by uz80as:
label;comment LABEL=5
TASM, for some reason, ignores the ‘2’ in the following expression and treats it as ‘*-3’, that is, the current program counter minus 3. We correctly parse it as ‘2*(-3)’.
.DB 2*-3
Something similar happens with the symbol * used for the current program counter with the multiplication operator.
These:
.DB ***, **2
are incorrectly parsed by TASM.
We correctly parse them as $*$ and $*2, that is, the current program counter multiplied by itself or by 2.
TASM does not:
.DB -+1
TASM says that it uses logical right shifts (inserting zeros) for the right shift operator, but it is actually using arithmetic right shift (the sign bit is extended) at least on x86 machines. We use arithmetic shift as well. So this results in $FF in TASM and uz80as, instead of $0F :
.DB -1>>28
Moreover, in uz80as only the least N bits of the second operand are used in the shifting operation, where N is the number of bits used by an integer on this machine, minus one.
For a system where an integer is 32 bits, N is 31.
This seems compatible with TASM.
TASM, on the other hand, shows a strange behavior. For example, this generates an object code of 256 bytes (?) without error:
.ORG 65536 .DB 1 .END
TASM accepts this as well without error:
.ORG -1 .DB 1 .END
.FILL.
Starting at .ORG 0, using .FILL -1 in TASM generates a 65535 length object file;
.FILL 65536 generates a zero length object file.
In uz80as, .FILL -1 issues an error;
.FILL 65536 correctly generates a 65536 length object file.
.MODULE and .LOCALLABELCHAR are not accepted at this moment by uz80as, but they are planned.
TASM accepts multiple .END directives and assembles code after it, at least in binary mode. We don’t accept that, but we accept programs without an .END directive.
ADD, ADC, SUB, SBC, AND, OR, XOR and CP with the A register as the first argument or without it (if the -x option is specified).
TASM sticks to the official Zilog syntax. See z80 target.
TASM accepts including files without enclosing them in double quotes:
#include file.asm
We always require the double quotes:
#include "file.asm"
For every instruction accepted for every target:
* marks undocumented instructions (selected with the -u command line option).
e is an expression. The number of bits actually used of the value depends on the instruction.
eN where N is a number, is an expression but only the N least significant bits are used.
bN where N is a number, is an expression which must evaluate to a value representable with N bits.
r8 is an expression. The distance from the program counter is calculated and only the least significant byte used.
The z80 target selects the Zilog Z80 instruction set.
These are the instructions accepted:
| ADC (HL) | ADC A,(HL) | ADC A,e8 | ADC HL,BC |
| ADC HL,DE | ADC HL,HL | ADC HL,SP | ADC e8 |
| ADD (HL) | ADD (IXi) | ADD (IYi) | * ADD A |
| * ADD A | ADD A | ADD A,(HL) | ADD A,(IXi) |
| ADD A,(IYi) | * ADD A,A | * ADD A,A | ADD A,A |
| * ADD A,B | * ADD A,B | ADD A,B | * ADD A,C |
| * ADD A,C | ADD A,C | * ADD A,D | * ADD A,D |
| ADD A,D | * ADD A,E | * ADD A,E | ADD A,E |
| ADD A,H | * ADD A,IXH | * ADD A,IXL | * ADD A,IYH |
| * ADD A,IYL | ADD A,L | ADD A,e8 | * ADD B |
| * ADD B | ADD B | * ADD C | * ADD C |
| ADD C | * ADD D | * ADD D | ADD D |
| * ADD E | * ADD E | ADD E | ADD H |
| ADD HL,BC | ADD HL,DE | ADD HL,HL | ADD HL,SP |
| ADD IX,BC | ADD IX,DE | ADD IX,IX | ADD IX,SP |
| * ADD IXH | * ADD IXL | ADD IY,BC | ADD IY,DE |
| ADD IY,IY | ADD IY,SP | * ADD IYH | * ADD IYL |
| ADD L | ADD e8 | AND (HL) | AND A,(HL) |
| AND A,e8 | AND e8 | BIT b3,(HL) | BIT b3,(IXi) |
| BIT b3,(IYi) | BIT b3,A | BIT b3,B | BIT b3,C |
| BIT b3,D | BIT b3,E | BIT b3,H | BIT b3,L |
| CALL C,e | CALL M,e | CALL NC,e | CALL NZ,e |
| CALL P,e | CALL PE,e | CALL PO,e | CALL Z,e |
| CALL e | CCF | CP (HL) | CP A,(HL) |
| CP A,e8 | CP e8 | CPD | CPDR |
| CPI | CPIR | CPL | DAA |
| DEC (HL) | DEC BC | DEC BC | DEC DE |
| DEC DE | DEC HL | DEC HL | DEC SP |
| DEC SP | DI | DJNZ r8 | EI |
| EX (SP),BC | EX (SP),DE | EX (SP),HL | EX (SP),HL |
| EX (SP),SP | EX AF,AF’ | EX DE,HL | EXX |
| HALT | IM t | * IN (C) | IN A,(C) |
| IN A,(e8) | IN B,(C) | IN C,(C) | IN D,(C) |
| IN E,(C) | IN F,(e) | IN H,(C) | IN L,(C) |
| INC (HL) | INC (IXi) | INC (IYi) | * INC A |
| * INC A | INC A | * INC B | * INC B |
| INC B | INC BC | INC BC | * INC C |
| * INC C | INC C | * INC D | * INC D |
| INC D | INC DE | INC DE | * INC E |
| * INC E | INC E | INC H | INC HL |
| INC HL | * INC IXH | * INC IXL | * INC IYH |
| * INC IYL | INC L | INC SP | INC SP |
| IND | INDR | INI | INIR |
| JP (BC) | JP (DE) | JP (HL) | JP (HL) |
| JP (SP) | JP C,e | JP M,e | JP NC,e |
| JP NZ,e | JP P,e | JP PE,e | JP PO,e |
| JP Z,e | JP e | JR C,r8 | JR NC,r8 |
| JR NZ,r8 | JR Z,r8 | JR r8 | LD (BC),A |
| LD (DE),A | LD (HL),A | LD (HL),B | LD (HL),C |
| LD (HL),D | LD (HL),E | LD (HL),H | LD (HL),L |
| LD (HL),e8 | LD (IXi),A | LD (IXi),B | LD (IXi),C |
| LD (IXi),D | LD (IXi),E | LD (IXi),H | LD (IXi),L |
| LD (IXi),e8 | LD (IYi),e8 | LD (e),A | LD (e),BC |
| LD (e),BC | LD (e),DE | LD (e),DE | LD (e),HL |
| LD (e),HL | LD (e),HL | LD (e),SP | LD (e),SP |
| LD A,(BC) | LD A,(DE) | LD A,(HL) | LD A,(e) |
| LD A,I | LD A,R | * LD A,e8 | * LD A,e8 |
| LD A,e8 | LD B,(HL) | LD B,(IXi) | LD B,(IYi) |
| * LD B,A | * LD B,A | LD B,A | * LD B,B |
| * LD B,B | LD B,B | * LD B,C | * LD B,C |
| LD B,C | * LD B,D | * LD B,D | LD B,D |
| * LD B,E | * LD B,E | LD B,E | LD B,H |
| * LD B,IXH | * LD B,IXL | * LD B,IYH | * LD B,IYL |
| LD B,L | * LD B,e8 | * LD B,e8 | LD B,e8 |
| LD BC,(e) | LD BC,(e) | LD BC,e | LD BC,e |
| LD C,(HL) | * LD C,e8 | * LD C,e8 | LD C,e8 |
| LD D,(HL) | * LD D,e8 | * LD D,e8 | LD D,e8 |
| LD DE,(e) | LD DE,(e) | LD DE,e | LD DE,e |
| LD E,(HL) | * LD E,e8 | * LD E,e8 | LD E,e8 |
| LD H,(HL) | LD H,e8 | LD HL,(e) | LD HL,(e) |
| LD HL,(e) | LD HL,e | LD HL,e | LD I,A |
| * LD IXH,e8 | * LD IXL,e8 | * LD IYH,e8 | * LD IYL,e8 |
| LD L,(HL) | LD L,e8 | LD R,A | LD SP,(e) |
| LD SP,(e) | LD SP,BC | LD SP,DE | LD SP,HL |
| LD SP,HL | LD SP,SP | LD SP,e | LD SP,e |
| LDD | LDDR | LDI | LDIR |
| NEG | NOP | OR (HL) | OR A,(HL) |
| OR A,e8 | OR e8 | OTDR | OTIR |
| * OUT (C),0 | OUT (C),A | OUT (C),B | OUT (C),C |
| OUT (C),D | OUT (C),E | OUT (C),H | OUT (C),L |
| OUT (e8),A | OUTD | OUTI | POP AF |
| POP BC | POP BC | POP DE | POP DE |
| POP HL | POP HL | POP SP | PUSH AF |
| PUSH BC | PUSH BC | PUSH DE | PUSH DE |
| PUSH HL | PUSH HL | PUSH SP | RES b3,(HL) |
| * RES b3,(IXi),A | * RES b3,(IXi),B | * RES b3,(IXi),C | * RES b3,(IXi),D |
| * RES b3,(IXi),E | * RES b3,(IXi),H | * RES b3,(IXi),L | RET |
| RET C | RET M | RET NC | RET NZ |
| RET P | RET PE | RET PO | RET Z |
| RETI | RETN | RL (HL) | RLA |
| RLC (HL) | RLC (IXi) | * RLC (IXi),A | * RLC (IXi),B |
| * RLC (IXi),C | * RLC (IXi),D | * RLC (IXi),E | * RLC (IXi),H |
| * RLC (IXi),L | RLC (IYi) | RLC A | RLC B |
| RLC C | RLC D | RLC E | RLC H |
| RLC L | RLCA | RLD | RR (HL) |
| RRA | RRC (HL) | RRCA | RRD |
| RST s | SBC (HL) | SBC A,(HL) | SBC A,e8 |
| SBC HL,BC | SBC HL,DE | SBC HL,HL | SBC HL,SP |
| SBC e8 | SCF | SET b3,(HL) | * SET b3,(IXi),A |
| * SET b3,(IXi),B | * SET b3,(IXi),C | * SET b3,(IXi),D | * SET b3,(IXi),E |
| * SET b3,(IXi),H | * SET b3,(IXi),L | SLA (HL) | * SLL (HL) |
| * SLL (IXi) | * SLL (IXi),A | * SLL (IXi),B | * SLL (IXi),C |
| * SLL (IXi),D | * SLL (IXi),E | * SLL (IXi),H | * SLL (IXi),L |
| * SLL (IYi) | * SLL A | * SLL B | * SLL C |
| * SLL D | * SLL E | * SLL H | * SLL L |
| SRA (HL) | SRL (HL) | SUB (HL) | SUB A,(HL) |
| SUB A,e8 | SUB e8 | XOR (HL) | XOR A,(HL) |
| XOR A,e8 | XOR e8 |
Where:
t is an expression which must evaluate to 0H, 8H, 10H, 18H, 20H, 28H, 30H or 38H.
s is an expression which must evaluate to 0, 1, or 2.
+ or - sign and an expression.
Note that in the official Zilog documentation, some of the arithmetic group of instructions take the A register as first argument: ADD, ADC and SBC.
Others do not: SUB, AND, OR, XOR and CP.
So you write:
ADD A,B
and do not write
ADD B
And you write:
SUB B
but do not write
SUB A,B
By default, it is an error to use the unofficial forms of these instructions, but you can enable them by specifying the -x option at the command line.
With this option enabled, you can write any of these instructions with or without the A register as the first argument, like this:
ADD A,B ADD B SUB A,B SUB B
For compatibility with other assemblers, it is better to keep the official syntax.
The hd64180 target selects the Hitachi HD64180 instruction set.
The instructions accepted are the same as for the z80 target (except undocumented instructions) plus these new instructions:
| IN0 A,(e8) | IN0 B,(e8) | IN0 C,(e8) | IN0 D,(e8) |
| IN0 E,(e8) | IN0 H,(e8) | IN0 L,(e8) | MLT BC |
| MLT DE | MLT HL | MLT SP | OTDM |
| OTDMR | OTIM | OTIMR | OUT0 (e8),A |
| OUT0 (e8),B | OUT0 (e8),C | OUT0 (e8),D | OUT0 (e8),E |
| OUT0 (e8),H | OUT0 (e8),L | SLP | TST (HL) |
| TST A | TST B | TST C | TST D |
| TST E | TST H | TST L | TST e8 |
| TSTIO e8 |
The gbcpu target selects the Sharp LR35902 CPU used in the Nintendo Gameboy.
These are the instructions accepted:
| ADC (HL) | ADC A,(HL) | ADC A,e8 | ADC e8 |
| ADD (HL) | ADD A | ADD A,(HL) | ADD A,A |
| ADD A,B | ADD A,C | ADD A,D | ADD A,E |
| ADD A,H | ADD A,L | ADD A,e8 | ADD B |
| ADD C | ADD D | ADD E | ADD H |
| ADD HL,BC | ADD HL,DE | ADD HL,HL | ADD HL,SP |
| ADD L | ADD SP,e8 | ADD e8 | AND (HL) |
| AND A,(HL) | AND A,e8 | AND e8 | BIT b3,(HL) |
| BIT b3,A | BIT b3,B | BIT b3,C | BIT b3,D |
| BIT b3,E | BIT b3,H | BIT b3,L | CALL C,e |
| CALL NC,e | CALL NZ,e | CALL Z,e | CALL e |
| CCF | CP (HL) | CP A,(HL) | CP A,e8 |
| CP e8 | CPL | DAA | DEC (HL) |
| DEC BC | DEC DE | DEC HL | DEC SP |
| DI | EI | HALT | INC (HL) |
| INC A | INC B | INC BC | INC C |
| INC D | INC DE | INC E | INC H |
| INC HL | INC L | INC SP | JP (HL) |
| JP C,e | JP NC,e | JP NZ,e | JP Z,e |
| JP e | JR C,r8 | JR NC,r8 | JR NZ,r8 |
| JR Z,r8 | JR r8 | LD (BC),A | LD (C),A |
| LD (DE),A | LD (HL),A | LD (HL),B | LD (HL),C |
| LD (HL),D | LD (HL),E | LD (HL),H | LD (HL),L |
| LD (HL),e8 | LD (HLD),A | LD (HLI),A | LD (e),A |
| LD (e),SP | LD A,(BC) | LD A,(C) | LD A,(DE) |
| LD A,(HL) | LD A,(HLD) | LD A,(HLI) | LD A,(e) |
| LD A,e8 | LD B,(HL) | LD B,A | LD B,B |
| LD B,C | LD B,D | LD B,E | LD B,H |
| LD B,L | LD B,e8 | LD BC,e | LD C,(HL) |
| LD C,e8 | LD D,(HL) | LD D,e8 | LD DE,e |
| LD E,(HL) | LD E,e8 | LD H,(HL) | LD H,e8 |
| LD HL,e | LD L,(HL) | LD L,e8 | LD SP,HL |
| LD SP,e | LDH (e8),A | LDH A,(e8) | LDHL SP,e8 |
| NOP | OR (HL) | OR A,(HL) | OR A,e8 |
| OR e8 | POP AF | POP BC | POP DE |
| POP HL | PUSH AF | PUSH BC | PUSH DE |
| PUSH HL | RES b3,(HL) | RET | RET C |
| RET NC | RET NZ | RET Z | RETI |
| RL (HL) | RLA | RLC (HL) | RLC A |
| RLC B | RLC C | RLC D | RLC E |
| RLC H | RLC L | RLCA | RR (HL) |
| RRA | RRC (HL) | RRCA | RST s |
| SBC (HL) | SBC A,(HL) | SBC A,e8 | SBC e8 |
| SCF | SET b3,(HL) | SLA (HL) | SRA (HL) |
| SRL (HL) | STOP | SUB (HL) | SUB A,(HL) |
| SUB A,e8 | SUB e8 | SWAP (HL) | XOR (HL) |
| XOR A,(HL) | XOR A,e8 | XOR e8 |
Where:
s is an expression which must evaluate to 0H, 8H, 10H, 18H, 20H, 28H, 30H or 38H.
The dp2200 target selects the Datapoint 2200 version I instruction set.
Important: the Datapoint 2200 version I can only address 8K at maximum but uz80as at this moment only imposes a 64K limit.
These are the instructions accepted:
| AC e8 | ACA | ACB | ACC |
| ACD | ACE | ACH | ACL |
| ACM | AD e8 | ADA | ADB |
| ADC | ADD | ADE | ADH |
| ADL | ADM | CALL e | CFC e |
| CFP e | CFS e | CFZ e | CP e8 |
| CPA | CPB | CPC | CPD |
| CPE | CPH | CPL | CPM |
| CTC e | CTP e | CTS e | CTZ e |
| EX ADR | EX BEEP | EX BSP | EX CLICK |
| EX COM1 | EX COM2 | EX COM3 | EX COM4 |
| EX DATA | EX DECK1 | EX DECK2 | EX RBK |
| EX REWND | EX SB | EX SF | EX STATUS |
| EX TSTOP | EX WBK | EX WRITE | HALT |
| INPUT | JFC e | JFP e | JFS e |
| JFZ e | JMP e | JTC e | JTP e |
| JTS e | JTZ e | LA e8 | LAB |
| LAC | LAD | LAE | LAH |
| LAL | LAM | LB e8 | LBA |
| LBC | LBD | LBE | LBH |
| LBL | LBM | LC e8 | LCA |
| LCB | LCD | LCE | LCH |
| LCL | LCM | LD e8 | LDA |
| LDB | LDC | LDE | LDH |
| LDL | LDM | LE e8 | LEA |
| LEB | LEC | LED | LEH |
| LEL | LEM | LH e8 | LHA |
| LHB | LHC | LHD | LHE |
| LHL | LHM | LL e8 | LLA |
| LLB | LLC | LLD | LLE |
| LLH | LLM | LMA | LMB |
| LMC | LMD | LME | LMH |
| LML | ND e8 | NDA | NDB |
| NDC | NDD | NDE | NDH |
| NDL | NDM | NOP | OR e8 |
| ORA | ORB | ORC | ORD |
| ORE | ORH | ORL | ORM |
| RETURN | RFC | RFP | RFS |
| RFZ | RTC | RTP | RTS |
| RTZ | SB e8 | SBA | SBB |
| SBC | SBD | SBE | SBH |
| SBL | SBM | SLC | SRC |
| SU e8 | SUA | SUB | SUC |
| SUD | SUE | SUH | SUL |
| SUM | XR e8 | XRA | XRB |
| XRC | XRD | XRE | XRH |
| XRL | XRM |
The dp2200ii target selects the Datapoint 2200 version II instruction set.
Important: the Datapoint 2200 version II can only address 16K at maximum but uz80as at this moment only imposes a 64K limit.
The instruction set accepted is the same as for the dp2200 target, plus these new instructions:
| ALPHA | BETA | DI | EI |
| POP | PUSH |
The i4004 target selects the Intel 4004 instruction set.
Important: the Intel 4004 can only address 4K at maximum but uz80as at this moment only imposes a 64K limit.
Note that the original Intel syntax was something like this:
LAB, ISZ 5 255 \ this is a comment
At this moment, you will need to translate that to a syntax acceptable by uz80as, for instance:
LAB: ISZ 5,255 ; this is a comment
However, we do accept the 0P, 1P, etc. notation to specify a register pair. These are the instructions accepted:
| ADD b4 | ADM | BBL b4 | CLB |
| CLC | CMA | CMC | DAA |
| DAC | DCL | FIM 0P,e8 | FIM 1P,e8 |
| FIM 2P,e8 | FIM 3P,e8 | FIM 4P,e8 | FIM 5P,e8 |
| FIM 6P,e8 | FIM 7P,e8 | FIM p,e8 | FIN 0P |
| FIN 1P | FIN 2P | FIN 3P | FIN 4P |
| FIN 5P | FIN 6P | FIN 7P | FIN p |
| IAC | INC b4 | ISZ b4,e8 | JCN b4,e8 |
| JIN 0P | JIN 1P | JIN 2P | JIN 3P |
| JIN 4P | JIN 5P | JIN 6P | JIN 7P |
| JIN p | JMS e | JUN e | KBP |
| LD b4 | LDM b4 | NOP | RAL |
| RAR | RD0 | RD1 | RD2 |
| RD3 | RDM | RDR | SBM |
| SRC 0P | SRC 1P | SRC 2P | SRC 3P |
| SRC 4P | SRC 5P | SRC 6P | SRC 7P |
| SRC p | STC | SUB b4 | TCC |
| TCS | WMP | WPM | WR0 |
| WR1 | WR2 | WR3 | WRM |
| WRR | XCH b4 |
Where:
p is an expression which must evaluate to 0,2,4,6,8,10,12 or 14.
The i4040 target selects the Intel 4040 instruction set.
Important: the Intel 4040 can only address 8K at maximum but uz80as at this moment only imposes a 64K limit.
The instruction set accepted is the same as for the i4004 target, plus these new instructions:
| AN6 | AN7 | BBS | DB0 |
| DB1 | DIN | EIN | HLT |
| LCR | OR4 | OR5 | RPM |
| SB0 | SB1 |
The i8008 target selects the Intel 8008 instruction set.
Important: the Intel 8008 can only address 16K at maximum but uz80as at this moment only imposes a 64K limit.
These are the instructions accepted:
| ACA | ACB | ACC | ACD |
| ACE | ACH | ACI e8 | ACL |
| ACM | ADA | ADB | ADC |
| ADD | ADE | ADH | ADI e8 |
| ADL | ADM | CAL e | CFC e |
| CFP e | CFS e | CFZ e | CPA |
| CPB | CPC | CPD | CPE |
| CPH | CPI e8 | CPL | CPM |
| CTC e | CTP e | CTS e | CTZ e |
| DCB | DCC | DCD | DCE |
| DCH | DCL | HLT | INB |
| INC | IND | INE | INH |
| INL | INP b3 | JFC e | JFP e |
| JFS e | JFZ e | JMP e | JTC e |
| JTP e | JTS e | JTZ e | LAB |
| LAC | LAD | LAE | LAH |
| LAI e8 | LAL | LAM | LBA |
| LBB | LBC | LBD | LBE |
| LBH | LBI e8 | LBL | LBM |
| LCA | LCB | LCC | LCD |
| LCE | LCH | LCI e8 | LCL |
| LCM | LDA | LDB | LDC |
| LDD | LDE | LDH | LDI e8 |
| LDL | LDM | LEA | LEB |
| LEC | LED | LEE | LEH |
| LEI e8 | LEL | LEM | LHA |
| LHB | LHC | LHD | LHE |
| LHH | LHI e8 | LHL | LHM |
| LLA | LLB | LLC | LLD |
| LLE | LLH | LLI e8 | LLL |
| LLM | LMA | LMB | LMC |
| LMD | LME | LMH | LMI e8 |
| LML | NDA | NDB | NDC |
| NDD | NDE | NDH | NDI e8 |
| NDL | NDM | NOP | ORA |
| ORB | ORC | ORD | ORE |
| ORH | ORI e8 | ORL | ORM |
| OUT k | RAL | RAR | RET |
| RFC | RFP | RFS | RFZ |
| RLC | RRC | RST b3 | RTC |
| RTP | RTS | RTZ | SBA |
| SBB | SBC | SBD | SBE |
| SBH | SBI e8 | SBL | SBM |
| SUA | SUB | SUC | SUD |
| SUE | SUH | SUI e8 | SUL |
| SUM | XRA | XRB | XRC |
| XRD | XRE | XRH | XRI e8 |
| XRL | XRM |
Where:
k is an expression which must evaluate to a value between 8 and 31.
The i8021 target selects the Intel 8021 instruction set.
These are the instructions accepted:
| ADD A,#e8 | ADD A,@R0 | ADD A,@R1 | ADD A,R0 |
| ADD A,R1 | ADD A,R2 | ADD A,R3 | ADD A,R4 |
| ADD A,R5 | ADD A,R6 | ADD A,R7 | ADDC A,#e8 |
| ADDC A,@R0 | ADDC A,@R1 | ADDC A,R0 | ADDC A,R1 |
| ADDC A,R2 | ADDC A,R3 | ADDC A,R4 | ADDC A,R5 |
| ADDC A,R6 | ADDC A,R7 | ANL A,#e8 | ANL A,@R0 |
| ANL A,@R1 | ANL A,R0 | ANL A,R1 | ANL A,R2 |
| ANL A,R3 | ANL A,R4 | ANL A,R5 | ANL A,R6 |
| ANL A,R7 | ANLD P4,A | ANLD P5,A | ANLD P6,A |
| ANLD P7,A | CALL e | CLR A | CLR C |
| CPL A | CPL C | DA A | DEC A |
| DJNZ R0,e8 | DJNZ R1,e8 | DJNZ R2,e8 | DJNZ R3,e8 |
| DJNZ R4,e8 | DJNZ R5,e8 | DJNZ R6,e8 | DJNZ R7,e8 |
| IN A,P0 | IN A,P1 | IN A,P2 | INC @R0 |
| INC @R1 | INC A | INC R0 | INC R1 |
| INC R2 | INC R3 | INC R4 | INC R5 |
| INC R6 | INC R7 | JC e8 | JMP e11 |
| JMPP @A | JNC e8 | JNT1 e8 | JNZ e8 |
| JT1 e8 | JTF e8 | JZ e8 | MOV @R0,#e8 |
| MOV @R0,A | MOV @R1,#e8 | MOV @R1,A | MOV A,#e8 |
| MOV A,@R0 | MOV A,@R1 | MOV A,R0 | MOV A,R1 |
| MOV A,R2 | MOV A,R3 | MOV A,R4 | MOV A,R5 |
| MOV A,R6 | MOV A,R7 | MOV A,T | MOV R0,#e8 |
| MOV R0,A | MOV R1,#e8 | MOV R1,A | MOV R2,#e8 |
| MOV R2,A | MOV R3,#e8 | MOV R3,A | MOV R4,#e8 |
| MOV R4,A | MOV R5,#e8 | MOV R5,A | MOV R6,#e8 |
| MOV R6,A | MOV R7,#e8 | MOV R7,A | MOV T,A |
| MOVD A,P4 | MOVD A,P5 | MOVD A,P6 | MOVD A,P7 |
| MOVD P4,A | MOVD P5,A | MOVD P6,A | MOVD P7,A |
| MOVP A,@A | NOP | NOP | ORL A,#e8 |
| ORL A,@R0 | ORL A,@R1 | ORL A,R0 | ORL A,R1 |
| ORL A,R2 | ORL A,R3 | ORL A,R4 | ORL A,R5 |
| ORL A,R6 | ORL A,R7 | ORLD P4,A | ORLD P5,A |
| ORLD P6,A | ORLD P7,A | OUTL P0,A | OUTL P1,A |
| OUTL P2,A | RET | RL A | RLC A |
| RR A | RRC A | STOP TCNT | STRT CNT |
| STRT T | SWAP A | XCH A,@R0 | XCH A,@R1 |
| XCH A,R0 | XCH A,R1 | XCH A,R2 | XCH A,R3 |
| XCH A,R4 | XCH A,R5 | XCH A,R6 | XCH A,R7 |
| XCHD A,@R0 | XCHD A,@R1 | XRL A,#e8 | XRL A,@R0 |
| XRL A,@R1 | XRL A,R0 | XRL A,R1 | XRL A,R2 |
| XRL A,R3 | XRL A,R4 | XRL A,R5 | XRL A,R6 |
| XRL A,R7 |
The i8022 target selects the Intel 8022 instruction set.
The instruction set accepted is the same as for the i8021 target, plus
these new instrucions:
| DIS I | DIS TCNTI | EN I | EN TCNTI |
| JNT0 e8 | JT0 e8 | RAD | RETI |
| SEL AN0 | SEL AN1 |
The i8041 target selects the Intel 8041 instruction set.
The instruction set accepted is the same as for the i8021 target, except that these instructions are removed:
| IN A,P0 | OUTL P0,A |
And these instructions are added:
| ANL P1,#e8 | ANL P2,#e8 | CLR F0 | CLR F1 |
| CPL F0 | CPL F1 | DEC R0 | DEC R1 |
| DEC R2 | DEC R3 | DEC R4 | DEC R5 |
| DEC R6 | DEC R7 | DIS I | DIS TCNTI |
| EN DMA | EN FLAGS | EN I | EN TCNTI |
| IN A,DBB | JB0 e8 | JB1 e8 | JB2 e8 |
| JB3 e8 | JB4 e8 | JB5 e8 | JB6 e8 |
| JB7 e8 | JF0 e8 | JF1 e8 | JNIBF e8 |
| JNT0 e8 | JOBF e8 | JT0 e8 | MOV A,PSW |
| MOV PSW,A | MOV STS,A | MOVP3 A,@A | ORL P1,#e8 |
| ORL P2,#e8 | OUT DBB,A | RETR | SEL RB0 |
| SEL RB1 |
The i8048 target selects the Intel 8048 instruction set.
The instruction set accepted is the same as for the i8041 target, except that these instructions are removed:
| EN FLAGS | EN DMA | IN A,DBB | JNIBF e8 |
| JOBF e8 | MOV STS,A | OUT DBB,A |
And these instructions are added:
| ANL BUS,#e8 | ENT0 CLK | INS A,BUS | JNI e8 |
| MOVX @R0,A | MOVX @R1,A | MOVX A,@R0 | MOVX A,@R1 |
| ORL BUS,#e8 | OUTL BUS,A | SEL MB0 | SEL MB1 |
The i8051 target selects the Intel 8051 instruction set.
These are the instructions accepted:
| ACALL e11 | ADD A,#e8 | ADD A,@R0 | ADD A,@R1 |
| ADD A,R0 | ADD A,R1 | ADD A,R2 | ADD A,R3 |
| ADD A,R4 | ADD A,R5 | ADD A,R6 | ADD A,R7 |
| ADD A,e8 | ADDC A,#e8 | ADDC A,e8 | AJMP e11 |
| ANL A,#e8 | ANL A,e8 | ANL C,/e8 | ANL C,e8 |
| ANL e,A | ANL e8,#e8 | CJNE @R0,#e8,r8 | CJNE @R1,#e8,r8 |
| CJNE A,#e8,r8 | CJNE A,e8,r8 | CJNE R0,#e8,r8 | CJNE R1,#e8,r8 |
| CJNE R2,#e8,r8 | CJNE R3,#e8,r8 | CJNE R4,#e8,r8 | CJNE R5,#e8,r8 |
| CJNE R6,#e8,r8 | CJNE R7,#e8,r8 | CLR A | CLR C |
| CLR e8 | CPL A | CPL C | CPL e8 |
| DA A | DEC @R0 | DEC @R1 | DEC A |
| DEC R0 | DEC R1 | DEC R2 | DEC R3 |
| DEC R4 | DEC R5 | DEC R6 | DEC R7 |
| DEC e8 | DIV AB | DJNZ R0,r8 | DJNZ R1,r8 |
| DJNZ R2,r8 | DJNZ R3,r8 | DJNZ R4,r8 | DJNZ R5,r8 |
| DJNZ R6,r8 | DJNZ R7,r8 | DJNZ e8,r8 | INC @R0 |
| INC @R1 | INC A | INC DPTR | INC R0 |
| INC R1 | INC R2 | INC R3 | INC R4 |
| INC R5 | INC R6 | INC R7 | INC e8 |
| JB e8,r8 | JBC e8,r8 | JC r8 | JMP @A+DPTR |
| JNB e8,r8 | JNC r8 | JNZ r8 | JZ r8 |
| LCALL e | LJMP e | MOV @R0,#e8 | MOV @R0,A |
| MOV @R0,e8 | MOV @R1,#e8 | MOV @R1,A | MOV @R1,e8 |
| MOV A,#e8 | MOV A,e8 | MOV C,e8 | MOV DPTR,#e8 |
| MOV R0,#e8 | MOV R0,A | MOV R0,e8 | MOV R1,#e8 |
| MOV R1,A | MOV R1,e8 | MOV R2,#e8 | MOV R2,A |
| MOV R2,e8 | MOV R3,#e8 | MOV R3,A | MOV R3,e8 |
| MOV R4,#e8 | MOV R4,A | MOV R4,e8 | MOV R5,#e8 |
| MOV R5,A | MOV R5,e8 | MOV R6,#e8 | MOV R6,A |
| MOV R6,e8 | MOV R7,#e8 | MOV R7,A | MOV R7,e8 |
| MOV e8,#e8 | MOV e8,@R0 | MOV e8,@R1 | MOV e8,A |
| MOV e8,C | MOV e8,R0 | MOV e8,R1 | MOV e8,R2 |
| MOV e8,R3 | MOV e8,R4 | MOV e8,R5 | MOV e8,R6 |
| MOV e8,R7 | MOV e8,e8 | MOVC A,@A+DPTR | MOVC A,@A+PC |
| MOVX @DPTR,A | MOVX @R0,A | MOVX @R1,A | MOVX A,@DPTR |
| MOVX A,@R0 | MOVX A,@R1 | MUL AB | NOP |
| ORL A,#e8 | ORL A,e8 | ORL C,/e8 | ORL C,e8 |
| ORL e8,#e8 | ORL e8,A | POP e8 | PUSH e8 |
| RET | RETI | RL A | RLC A |
| RR A | RRC A | SETB C | SETB e8 |
| SJMP r8 | SUBB A,#e8 | SUBB A,e8 | SWAP A |
| XCH A,e8 | XCHD A,@R0 | XCHD A,@R1 | XRL A,#e8 |
| XRL A,e8 | XRL e8,#e8 | XRL e8,A |
The i8080 target selects the Intel 8080.
These are the instructions accepted:
| ACI e8 | ADD A | ADD B | ADD C |
| ADD D | ADD E | ADD H | ADD L |
| ADD M | ADI e8 | ANI e8 | CALL e |
| CC e | CM e | CMA | CMC |
| CNC e | CNZ e | CP e | CPE e |
| CPI e8 | CPO e | CZ e | DAA |
| DAD B | DAD D | DAD H | DAD SP |
| DCR A | DCR B | DCR C | DCR D |
| DCR E | DCR H | DCR L | DCR M |
| DCX B | DCX D | DCX H | DCX SP |
| DI | EI | HLT | IN e8 |
| INR A | INR B | INR C | INR D |
| INR E | INR H | INR L | INR M |
| INX B | INX D | INX H | INX SP |
| JC e | JM e | JMP e | JNC e |
| JNZ e | JP e | JPE e | JPO e |
| JZ e | LDA e | LHLD e | LXI B,e |
| LXI D,e | LXI H,e | LXI SP,e | MOV A,M |
| MOV B,A | MOV B,B | MOV B,C | MOV B,D |
| MOV B,E | MOV B,H | MOV B,L | MOV B,M |
| MOV C,M | MOV D,M | MOV E,M | MOV H,M |
| MOV L,M | MOV M,A | MOV M,B | MOV M,C |
| MOV M,D | MOV M,E | MOV M,H | MOV M,L |
| MVI A,e8 | MVI B,e8 | MVI C,e8 | MVI D,e8 |
| MVI E,e8 | MVI H,e8 | MVI L,e8 | MVI M,e8 |
| NOP | ORI e8 | OUT e8 | PCHL |
| POP B | POP D | POP H | POP PSW |
| RAL | RAR | RC | RET |
| RLC | RM | RNC | RNZ |
| RP | RPE | RPO | RRC |
| RST b3 | RZ | SBI e8 | SHLD e |
| SPHL | STA e | STAX B | STAX D |
| STC | SUI e8 | XCHG | XRI e8 |
| XTHL |
The i8085 target selects the Intel 8085.
The instruction set accepted is the same as for the i8080 target, plus these new instructions:
| * ARHL | * DSUB | * JK e | * JNK e |
| * JNUI e | * JNX5 e | * JUI e | * JX5 e |
| * LDHI e8 | * LDSI e8 | * LHLX | * RDEL |
| RIM | * RSTV | * SHLX | SIM |
Where:
JNX5 and JNUI are alternative names for the JNK instruction.
JX5 and JUI are alternative names for the JK instruction.
The mos6502 target selects the MOS Technology 6502.
These are the instructions accepted:
| ADC #e8 | ADC (e8),Y | ADC (e8,X) | ADC >e16 |
| ADC >e16,X | ADC e | ADC e,X | ADC e,Y |
| AND #e8 | AND (e8),Y | AND (e8,X) | AND >e16 |
| AND >e16,X | AND e | AND e,X | AND e,Y |
| ASL >e16 | ASL >e16,X | ASL A | ASL e |
| ASL e,X | BCC r8 | BCS r8 | BEQ r8 |
| BIT >e16 | BIT e | BMI r8 | BNE r8 |
| BPL r8 | BRK | BVC r8 | BVS r8 |
| CLC | CLD | CLI | CLV |
| CMP #e8 | CMP (e8),Y | CMP (e8,X) | CMP >e16 |
| CMP >e16,X | CMP e | CMP e,X | CMP e,Y |
| CPX #e8 | CPX >e16 | CPX e | CPY #e8 |
| CPY >e16 | CPY e | DEC >e16 | DEC >e16,X |
| DEC e | DEC e,X | DEX | DEY |
| EOR #e8 | EOR (e8),Y | EOR (e8,X) | EOR >e16 |
| EOR >e16,X | EOR e | EOR e,X | EOR e,Y |
| INC >e16 | INC >e16,X | INC e | INC e,X |
| INX | INY | JMP (e) | JMP e |
| JSR e | LDA #e8 | LDA (e8),Y | LDA (e8,X) |
| LDA >e16 | LDA >e16,X | LDA e | LDA e,X |
| LDA e,Y | LDX #e8 | LDX >e16 | LDX >e16,Y |
| LDX e | LDX e,Y | LDY #e8 | LDY >e16 |
| LDY >e16,X | LDY e | LDY e,X | LSR >e16 |
| LSR >e16,X | LSR A | LSR e | LSR e,X |
| NOP | ORA #e8 | ORA (e8),Y | ORA (e8,X) |
| ORA >e16 | ORA >e16,X | ORA e | ORA e,X |
| ORA e,Y | PHA | PHP | PLA |
| PLP | ROL >e16 | ROL >e16,X | ROL A |
| ROL e | ROL e,X | ROR >e16 | ROR >e16,X |
| ROR A | ROR e | ROR e,X | RTI |
| RTS | SBC #e8 | SBC (e8),Y | SBC (e8,X) |
| SBC >e16 | SBC >e16,X | SBC e | SBC e,X |
| SBC e,Y | SEC | SED | SEI |
| STA (e8),Y | STA (e8,X) | STA >e16 | STA >e16,X |
| STA e | STA e,X | STA e,Y | STX >e16 |
| STX e | STX e8,Y | STY >e16 | STY e |
| STY e8,X | TAX | TAY | TSX |
| TXA | TXS | TYA |
Where > forces the use of a 16 bit address.
The r6501 target selects the Rockwell R6501.
The instruction set accepted is the same as for the mos6502 target, plus these new instructions:
| BBR0 e8,r8 | BBR1 e8,r8 | BBR2 e8,r8 | BBR3 e8,r8 |
| BBR4 e8,r8 | BBR5 e8,r8 | BBR6 e8,r8 | BBR7 e8,r8 |
| BBS0 e8,r8 | BBS1 e8,r8 | BBS2 e8,r8 | BBS3 e8,r8 |
| BBS4 e8,r8 | BBS5 e8,r8 | BBS6 e8,r8 | BBS7 e8,r8 |
| RMB0 e8 | RMB1 e8 | RMB2 e8 | RMB3 e8 |
| RMB4 e8 | RMB5 e8 | RMB6 e8 | RMB7 e8 |
| SMB0 e8 | SMB1 e8 | SMB2 e8 | SMB3 e8 |
| SMB4 e8 | SMB5 e8 | SMB6 e8 | SMB7 e8 |
The g65sc02 target selects the California Micro Devices G65SC02.
The instruction set accepted is the same as for the mos6502 target, plus these new instructions:
| ADC (e8) | AND (e8) | BIT #e8 | BIT >e16,X |
| BIT e,X | BRA r8 | CMP (e8) | DEC A |
| EOR (e8) | INC A | JMP (e,X) | LDA (e8) |
| ORA (e8) | PHX | PHY | PLX |
| PLY | SBC (e8) | STA (e8) | STZ >e16 |
| STZ >e16,X | STZ e | STZ e,X | TRB >e16 |
| TRB e | TSB >e16 | TSB e |
Where > forces the use of a 16 bit address.
The r65c02 target selects the Rockwell R65C02.
The instruction set accepted is the same as for the mos6502 target, plus the added instructions of the r6501 and g65sc02 targets.
The r65c29 target selects the Rockwell R65C29, R65C00/21.
The instruction set accepted is the same as for the r65c02 target, plus these new instructions:
| MUL |
The w65c02s target selects the Western Design Center W65C02S.
The instruction set accepted is the same as for the r65c02 target, plus these new instructions:
| STP | WAI |
The mc6800 target selects the Motorola 6800.
These are the instructions accepted:
| ABA | ADCA #e8 | ADCA >e16 | ADCA e |
| ADCA e8,X | ADCB #e8 | ADCB >e16 | ADCB e |
| ADCB e8,X | ADDA #e8 | ADDA >e16 | ADDA e |
| ADDA e8,X | ADDB #e8 | ADDB >e16 | ADDB e |
| ADDB e8,X | ANDA #e8 | ANDA >e16 | ANDA e |
| ANDA e8,X | ANDB #e8 | ANDB >e16 | ANDB e |
| ANDB e8,X | ASL e16 | ASL e8,X | ASLA |
| ASLB | ASR e16 | ASR e8,X | ASRA |
| ASRB | BCC r8 | BCS r8 | BEQ r8 |
| BGE r8 | BGT r8 | BHI r8 | BITA #e8 |
| BITA >e16 | BITA e | BITA e8,X | BITB #e8 |
| BITB >e16 | BITB e | BITB e8,X | BLE r8 |
| BLS r8 | BLT r8 | BMI r8 | BNE r8 |
| BPL r8 | BRA r8 | BSR r8 | BVC r8 |
| BVS r8 | CBA | CLC | CLI |
| CLR e16 | CLR e8,X | CLRA | CLRB |
| CLV | CMPA #e8 | CMPA >e16 | CMPA e |
| CMPA e8,X | CMPB #e8 | CMPB >e16 | CMPB e |
| CMPB e8,X | COM e16 | COM e8,X | COMA |
| COMB | CPX #e16 | CPX >e16 | CPX e |
| CPX e8,X | DAA | DEC e16 | DEC e8,X |
| DECA | DECB | DES | DEX |
| EORA #e8 | EORA >e16 | EORA e | EORA e8,X |
| EORB #e8 | EORB >e16 | EORB e | EORB e8,X |
| INC e16 | INC e8,X | INCA | INCB |
| INS | INX | JMP e16 | JMP e8,X |
| JSR e16 | JSR e8,X | LDAA #e8 | LDAA >e16 |
| LDAA e | LDAA e8,X | LDAB #e8 | LDAB >e16 |
| LDAB e | LDAB e8,X | LDS #e16 | LDS >e16 |
| LDS e | LDS e8,X | LDX #e16 | LDX >e16 |
| LDX e | LDX e8,X | LSR e16 | LSR e8,X |
| LSRA | LSRB | NEG e16 | NEG e8,X |
| NEGA | NEGB | NOP | ORAA #e8 |
| ORAA >e16 | ORAA e | ORAA e8,X | ORAB #e8 |
| ORAB >e16 | ORAB e | ORAB e8,X | PSHA |
| PSHB | PULA | PULB | ROL e16 |
| ROL e8,X | ROLA | ROLB | ROR e16 |
| ROR e8,X | RORA | RORB | RTI |
| RTS | SBA | SBCA #e8 | SBCA >e16 |
| SBCA e | SBCA e8,X | SBCB #e8 | SBCB >e16 |
| SBCB e | SBCB e8,X | SEC | SEI |
| SEV | STAA >e16 | STAA e | STAA e8,X |
| STAB >e16 | STAB e | STAB e8,X | STS >e16 |
| STS e | STS e8,X | STX >e16 | STX e |
| STX e8,X | SUBA #e8 | SUBA >e16 | SUBA e |
| SUBA e8,X | SUBB #e8 | SUBB >e16 | SUBB e |
| SUBB e8,X | SWI | TAB | TAP |
| TBA | TPA | TST e16 | TST e8,X |
| TSTA | TSTB | TSX | TXS |
| WAI |
Where > forces the use of a 16 bit address.
The mc6801 target selects the Motorola 6801.
The instruction set accepted is the same as for the mc6800 target, plus these new instructions:
| ABX | ADDD #e16 | ADDD >e16 | ADDD e |
| ADDD e8,X | ASLD | BHS r8 | BLO r8 |
| BRN r8 | JSR >e16 | JSR e | LDD #e16 |
| LDD >e16 | LDD e | LDD e8,X | LSL e16 |
| LSL e8,X | LSLD | LSRD | MUL |
| PSHX | PULX | STD >e16 | STD e |
| STD e8,X | SUBD #e16 | SUBD >e16 | SUBD e |
| SUBD e8,X |
The m68hc11 target selects the Motorola 68HC11.
The instruction set accepted is the same as for the mc6801 target, plus these new instructions:
| ABY | ADCA e8,Y | ADCB e8,Y | ADDA e8,Y |
| ADDB e8,Y | ADDD e8,Y | ANDA e8,Y | ANDB e8,Y |
| ASL e8,Y | ASR e8,Y | BCLR e8,X,e8 | BCLR e8,Y,e8 |
| BCLR e8,e8 | BITA e8,Y | BITB e8,Y | BRCLR e8,X,e8,r8 |
| BRCLR e8,Y,e8,r8 | BRCLR e8,e8,r8 | BRSET e8,X,e8,r8 | BRSET e8,Y,e8,r8 |
| BRSET e8,e8,r8 | BSET e8,X,e8 | BSET e8,Y,e8 | BSET e8,e8 |
| CLR e8,Y | CMPA e8,Y | CMPB e8,Y | COM e8,Y |
| CPD #e16 | CPD >e16 | CPD e | CPD e8,X |
| CPD e8,Y | CPX e8,Y | CPY #e16 | CPY >e16 |
| CPY e | CPY e8,X | CPY e8,Y | DEC e8,Y |
| DEY | EORA e8,Y | EORB e8,Y | FDIV |
| IDIV | INC e8,Y | INY | JMP e8,Y |
| JSR e8,Y | LDAA e8,Y | LDAB e8,Y | LDD e8,Y |
| LDS e8,Y | LDX e8,Y | LDY #e16 | LDY >e16 |
| LDY e | LDY e8,X | LDY e8,Y | LSL e8,Y |
| LSLA | LSLB | LSR e8,Y | NEG e8,Y |
| ORAA e8,Y | ORAB e8,Y | PSHY | PULY |
| ROL e8,Y | ROR e8,Y | SBCA e8,Y | SBCB e8,Y |
| STAA e8,Y | STAB e8,Y | STD e8,Y | STOP |
| STS e8,Y | STX e8,Y | STY >e16 | STY e |
| STY e8,X | STY e8,Y | SUBA e8,Y | SUBB e8,Y |
| SUBD e8,Y | TEST | TST e8,Y | TSY |
| TYS | XGDX | XGDY |
The rca1802 target selects the RCA 1802.
These are the instructions accepted:
| ADC | ADCI e8 | ADD | ADI e8 |
| AND | ANI e8 | B1 e8 | B2 e8 |
| B3 e8 | B4 e8 | BDF e8 | BGE e8 |
| BL e8 | BM e8 | BN1 e8 | BN2 e8 |
| BN3 e8 | BN4 e8 | BNF e8 | BNQ e8 |
| BNZ e8 | BPZ e8 | BQ e8 | BR e8 |
| BZ e8 | DEC b4 | DIS | GHI b4 |
| GLO b4 | IDL | INC b4 | INP p |
| IRX | LBDF e | LBNF e | LBNQ e |
| LBNZ e | LBQ e | LBR e | LBZ e |
| LDA b4 | LDI e8 | LDN m | LDX |
| LDXA | LSDF | LSIE | LSKP |
| LSNF | LSNQ | LSNZ | LSQ |
| LSZ | MARK | NBR e8 | NLBR e |
| NOP | OR | ORI e8 | OUT p |
| PHI b4 | PLO b4 | REQ | RET |
| RSHL | RSHR | SAV | SD |
| SDB | SDBI e8 | SDI e8 | SEP b4 |
| SEQ | SEX b4 | SHL | SHLC |
| SHR | SHRC | SKP | SM |
| SMB | SMBI e8 | SMI e8 | STR b4 |
| STXD | XOR | XRI e8 |
Where:
m is an expression wich must evaluate to a value between 1 and 15.
p is an expression which must evaluate to a value between 1 and 7.
This manual is for uz80as (Micro Z80 assembler) version 2.02 (updated 19 June 2023).
Copyright © 2023 Jorge Giner Cordero
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.